1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular, to the semiconductor integrated circuit device including a flip-flop circuit.
2. Description of the Related Art
Conventionally, a flip-flop circuit is widely used in an integrated circuit such as LSI. And in general, power consumption of the flip-flop circuit in the integrated circuit occupies a large part of the power consumption of the entire integrated circuit. For that reason, reduction in the power consumption of the flip-flop circuit leads to reduction in the power consumption of the entire integrated circuit so as to consequently reduce heat generation of the integrated circuit. Examples of such a semiconductor integrated circuit device including the flip-flop circuit include those proposed in Document 1 (Japanese Patent Laid-Open No. 2004-056667) and Document 2 (Peiyi Zhao, Tarek K. Darwish, and Magdy A. Bayoumi, “High-Performance and Low-Power Conditional Discharge Flip-Flop.” IEEE TRANCEACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 12, NO. 5, MAY 2004 p 477 to p 484).
The semiconductor integrated circuit device proposed in Document 1 uses a clock control circuit. In the case where an input signal and an output signal of the flip-flop circuit are the same logical value, it suppresses operation of the flip-flop circuit by keeping an internal clock signal at a fixed value so as to realize the reduction in power consumption.
The semiconductor integrated circuit device proposed in Document 2 has a discharge control circuit inserted on a discharge path significantly consuming electric power. In the case where an input signal and an output signal of the flip-flop circuit are the same logical value, it puts the discharge control circuit in an open state and maintains electric charge accumulated in parasitic capacitance so as to realize the reduction in power consumption.
In the case of the semiconductor integrated circuit device proposed in Document 1, however, the clock control circuit exerts the aforementioned operational control to the flip-flop circuit. Therefore, it has a problem that the clock-output delay and setup time becomes larger so that operation speed of the entire semiconductor integrated circuit device consequently decreases.
In the case of the semiconductor integrated circuit device proposed in Document 2, the discharge control circuit is inserted on the discharge path. Therefore, it has a problem that an amount of currents on the discharge path in state transition is reduced and operation speed of the entire circuit is thereby decreased so that the circuit size (transistor size) must be enlarged to maintain the operation speed of the entire circuit.